Hello all;
i need help for synthesize a combine project with EDK in ISE.
i have a project in ISE and i want to add ethernetmaclite from EDK to it.i'm follow below steps(i'm trying to make bit file without *.elf for first time.):

1- create a project in ISE and synthesized it.
2- add "Embedde Processor" source from "Project/Add Source".
3- start BSB feom EDK and create a project with Micro Blaze in EDk.
4- add IP "XPS UART (Lite)" and "XPS 10/100 Ethernet MAC Lite" from "IP Catalog" tab.
5- connect these IP to "MB_PLB" in "Bus Interface" tab.
6- push "Generate Addresses" in "Address" tab.
7- add external ports with "New Connection" and "Make External" in "Ports" tab.
8- from "Software/Software Platform Settings/OS and Lib Configuration" set "std_in" and "std_out" to "xps_uart_lite0".
9- click "Hardware/Generate Netlist" for generating netlist.
10- in ISE,click on EDK (*.xmp) and in lower window click on "View HDL Instantiation Template".
11- then add declaration and instantiation in top level VHDL file and complete portmap.

when synthesize project(in ISE), view this message in "Low Level Synthesis":

Mapping all equations...
ERROR:Xst:2937 - Processing TIMESPEC OFFSET: No signal name xps_ethernetlite_0_PHY_rx_clk_pin found in design.
ERROR:Xst:1489 - Constraint annotation failed.


top file entity is:

entity test_app is
port (

clk : in std_logic ;
reset : in std_logic ;
rs232_rx : in std_logic ;
rs232_tx : out std_logic ;
eth_rx_dv : in std_logic ;
receive_clk : in std_logic ;
eth_rx_err : in std_logic ;
transmit_clk : in std_logic ;
eth_tx_en : out std_logic ;
eth_tx_data : out std_logic_vector(3 downto 0) ;
eth_col : in std_logic ;
eth_crs : in std_logic ;
eth_reset : out std_logic ;
eth_rx_data : in std_logic_vector(3 downto 0) ;
eth_mdc : out std_logic ;
eth_mdio : inout std_logic ;
in_data : in std_logic_vector(7 downto 0)

) ;
end test_app ;


and port map is:


Inst_system: system PORT MAP(
fpga_0_clk_1_sys_clk_pin => clk,
fpga_0_rst_1_sys_rst_pin => reset,
xps_uartlite_0_RX_pin => rs232_rx,
xps_uartlite_0_TX_pin => rs232_tx,
xps_ethernetlite_0_PHY_tx_clk_pin => transmit_clk,
xps_ethernetlite_0_PHY_rx_clk_pin => receive_clk,
xps_ethernetlite_0_PHY_crs_pin => eth_crs,
xps_ethernetlite_0_PHY_dv_pin => eth_rx_dv,
xps_ethernetlite_0_PHY_rx_data_pin => eth_rx_data,
xps_ethernetlite_0_PHY_col_pin => eth_col,
xps_ethernetlite_0_PHY_rx_er_pin => eth_rx_err,
xps_ethernetlite_0_PHY_rst_n_pin => eth_reset,
xps_ethernetlite_0_PHY_tx_en_pin => eth_tx_en,
xps_ethernetlite_0_PHY_tx_data_pin => eth_tx_data,
xps_ethernetlite_0_PHY_MDC_pin => eth_mdc,
xps_ethernetlite_0_PHY_MDIO_pin => eth_mdio
);


please help me for debug project.
best regards,Amir